The present invention is directed, in general, to a method for manufacturing a semiconductor device and, more specifically, to a method for controlling a critical dimension (CD) in an etch process.
Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds, and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
One important process requiring careful inspection is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (i.e., a photoresist layer), which has been previously coated on a layer, such as a polysilicon or metal layer formed on the silicon wafer. The transfer of the mask pattern onto the photoresist layer is conventionally performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. Design rules set limits on critical dimension (xe2x80x9cCDxe2x80x9d), which may be defined as any linewidth of interest in a device containing a number of different linewidths. The CD for most features in ultra large scale integration applications is on the order of a fraction of a micron, however, it generally depends on the specific feature.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of surface features"" CD, as well as their cross-sectional shape (xe2x80x9cprofilexe2x80x9d) are becoming increasingly important. Deviations of a feature""s CD and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature""s CD and profile may indicate processing problems, such as stepper defocusing or photoresist loss due to over-exposure.
In an effort to reduce the aforementioned deviations in post-etch feature CD, the art currently calculates the etch bias of the process. Etch bias is defined as the amount of change in the final dimensions of the feature relative to the as-patterned dimensions of the photoresist used to form the feature. In other words the etch bias places a value on the accuracy of the pattern transfer from the lithography process to the etch process. Currently, for pattern levels where the CD bias is controlled by changes to the etch process for each lot, etch bias prediction is based on the photoresist CD alone. Generally, this photoresist CD is measured using conventional measurement techniques, such as a scanning electron microscope (SEM) or other technique. Unfortunately, however, photoresist CD alone, and especially that obtained using SEM, provides inconsistent data. If used, the inconsistent data often compromises the manufacturing process.
Accordingly, what is needed in the art is a simple, cost-effective methodology for fast and meaningful identification and correction of CD variation.
To address the above-discussed deficiencies of the prior art, the present invention provides a method for determining etch process conditions in an etch process. In one embodiment of the invention, the method for determining the etch process conditions includes obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer, and then obtaining an estimated etch process condition of the patterned resist layer using the resist profile data and critical dimension data.
In an alternative embodiment, the present invention provides a method for controlling a critical dimension (CD) in an etch process. Among other things, the method for controlling a CD in an etch process includes, obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer. From the resist profile data, the method generates an empirical model, and then uses the empirical model to configure an etch process for the patterned resist layer.
Further, the present invention provides a method for manufacturing a semiconductor device using the aforementioned method for controlling a CD in an etch process. In addition to that disclosed above, the method for manufacturing a semiconductor device includes using the empirical model to adjust an etch process applied to the patterned resist layer to form a trimmed patterned resist layer and then forming a structure by etching a material exposed by the trimmed patterned resist.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.